DATA_FORMAT_18_BIT=LOWER_18_BITS_VALID, CSC_DATA_SWIZZLE=NO_SWAP, LCD_DATABUS_WIDTH=16_BIT, DATA_FORMAT_24_BIT=ALL_24_BITS_VALID, WORD_LENGTH=16_BIT, DATA_SHIFT_DIR=TXDATA_SHIFT_LEFT, INPUT_DATA_SWIZZLE=NO_SWAP
LCDIF General Control Register
| RUN | When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display |
| DATA_FORMAT_24_BIT | Used only when WORD_LENGTH = 3, i 0 (ALL_24_BITS_VALID): Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. 1 (DROP_UPPER_2_BITS_PER_BYTE): Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. |
| DATA_FORMAT_18_BIT | Used only when WORD_LENGTH = 2, i.e. 18-bit. 0 (LOWER_18_BITS_VALID): Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. 1 (UPPER_18_BITS_VALID): Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. |
| DATA_FORMAT_16_BIT | When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format |
| MASTER | Set this bit to make the LCDIF act as a bus master |
| ENABLE_PXP_HANDSHAKE | If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on |
| WORD_LENGTH | Input data format. 0 (16_BIT): Input data is 16 bits per pixel. 1 (8_BIT): Input data is 8 bits wide. 2 (18_BIT): Input data is 18 bits per pixel. 3 (24_BIT): Input data is 24 bits per pixel. |
| LCD_DATABUS_WIDTH | LCD Data bus transfer width. 0 (16_BIT): 16-bit data bus mode. 1 (8_BIT): 8-bit data bus mode. 2 (18_BIT): 18-bit data bus mode. 3 (24_BIT): 24-bit data bus mode. |
| CSC_DATA_SWIZZLE | This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus 0 (NO_SWAP): No byte swapping.(Little endian) 1 (BIG_ENDIAN_SWAP): Big Endian swap (swap bytes 0,3 and 1,2). 2 (HWD_SWAP): Swap half-words. 3 (HWD_BYTE_SWAP): Swap bytes within each half-word. |
| INPUT_DATA_SWIZZLE | This field specifies how to swap the bytes fetched by the bus master interface 0 (NO_SWAP): No byte swapping.(Little endian) 1 (BIG_ENDIAN_SWAP): Big Endian swap (swap bytes 0,3 and 1,2). 2 (HWD_SWAP): Swap half-words. 3 (HWD_BYTE_SWAP): Swap bytes within each half-word. |
| DOTCLK_MODE | Set this bit to 1 to make the hardware go into the DOTCLK mode, i |
| BYPASS_COUNT | When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out |
| SHIFT_NUM_BITS | The data to be transmitted is shifted left or right by this number of bits. |
| DATA_SHIFT_DIR | Use this bit to determine the direction of shift of transmit data. 0 (TXDATA_SHIFT_LEFT): Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. 1 (TXDATA_SHIFT_RIGHT): Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. |
| CLKGATE | This bit must be set to zero for normal operation |
| SFTRST | This bit must be set to zero to enable normal operation of the LCDIF |